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Agilent HDMP-1032A/1034A Transmitter/Receiver Chip Set
Data Sheet
Features * 3.3 V supply, low power dissipation 660 mW Tx, 792 mW Rx * On-chip encode/decode using Conditional Inversion Master Transition (CIMT) protocol * 1:N broadcast ready configurable receiver inputs allow multi-point data broadcast using a single transmitter * Parallel Automatic Synchronization System (PASS) allows receiver to read recovered words with local reference clock * Robust simplex mode * Wide range serial rate 260-1400 MBaud (user selectable) * 5 V tolerant TTL interface 16 or 17 Bits wide * Low cost 64 pin plastic package 14x14 mm2 PQFP Applications * Cellular base station * ATM switch * Backplane/bus extender * Video, image acquisition * Point to point data link * Implement SCI-FI standard
1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate.
Description The HDMP-1032A transmitter and HDMP-1034A receiver are used together to build a high-speed data link for point-to-point communication. These silicon bipolar transmitter and receiver chips are housed in standard plastic 64 pin PQFP packages. From the user's viewpoint, these products can be thought of as a "virtual ribbon cable" interface for the transmission of data and control words. A parallel word loaded into the Tx (transmitter) chip is delivered to the Rx (receiver) chip over a serial channel and is then reconstructed into its original parallel form. The channel can be either a coaxial copper cable or optical link The chip set hides from the user the complexity of encoding, multiplexing, clock extraction, demultiplexing and decoding. The CIMT encoding scheme used ensures the DC balance of the serial line. When data or control words are not being sent the transmitter sends idle words. The serial data rate of the Tx/Rx link is selectable in three ranges and extends from 208 to 1120 Mbit/s. This translates into an encoded serial rate of 260 to 1400 MBaud. The parallel data interface is 16 bit TTL. A flag bit is also present and can be used as an extra 17th bit under the user's control. This bit can be used as an even or odd word indicator for dual-word transmission. The encoding of the flag bit can be scrambled to reduce the probability of erroneous word alignment. A user control space is also provided. If TXCNTL is asserted on the Tx chip, the least significant 14 bits of the data will be sent and the RXCNTL line on the Rx chip will indicate the data is a Control Word. At the Rx, the PASS feature allows the recovered words to be clocked out with the local
REFCLK. This feature is particularly useful when the Tx clock and REFCLK are synchronous. The PASS system also supports synchronization of multiple channels. The chipset is compatible with previous versions of the G-Link chipset (HDMP-10x2/10x4) provided the latter are used in 16 bit Simplex with Periodic Sync Pulse or External Reference Oscillator Mode (Simplex Method II or III).
Table of Contents Topic Page Typical Applications ................................................................................................... 3 Setting the Operating Data Rate Range .................................................................. 4 Transmitter Block Diagram ....................................................................................... 5 Receiver Block Diagram ............................................................................................ 6 Parallel Automatic Synchronization System .......................................................... 7 Transmitter Timing .................................................................................................... 10 Receiver Timing ........................................................................................................... 11 DC Electrical Specifications ..................................................................................... 12 AC Electrical Specifications ..................................................................................... 12 TXCLK and REFCLK Requirements ........................................................................... 13 Absolute Maximum Ratings ...................................................................................... 13 Thermal Characteristics ............................................................................................ 14 I/O Type Definitions .................................................................................................... 14 Pin-Out Diagrams ........................................................................................................ 15 Transmitter Pin Definitions ........................................................................................ 16 Receiver Pin Definitions ............................................................................................ 18 Mechanical Dimensions ............................................................................................ 21 Appendix: Internal Architecture Information Line Code Description ................................................................................................ 22 Data, Control, and Idle Word Codes ........................................................................ 22 Tx Operation Principles - Encoding & Phase Lock Loop .................................... 24 Rx Operation Principles - Decoding & Phase Lock Loop .................................... 25 Integrator Capacitor & Power Supply Bypassing/Grounding ................................................................................................. 26 TTL and High Speed I/O ............................................................................................. 26 Data Bus Line/Broadcast Transmission ................................................................. 27 Nomenclature Changes between HDMP-1032A/34A and HDMP-1022/24 .................................................................... 30 Pin Cross Reference Table ........................................................................................ 31
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Tx TXCLK
Rx
RXCLK0/1 REFCLK
A) 16 BIT SIMPLEX TRANSMISSION
Tx TXCLK
Rx HDMP-1022 fig 1a
RXCLK0/1 REFCLK
Typical Applications The HDMP-1032A/1034A chipset was designed for ease of use and flexibility. The customer can tailor the use of this product through the configuration of the link based on specific system requirements and application needs. Typical applications range from backplane serialization and bus extension to cellular base stations. All modes are built up from the basic simplex transmission mode as shown in Figure 1a. For digital video transmission, simplex links are common. The HDMP-1032A/1034A chipset can transmit 16 bits of parallel data in standard or broadcast simplex mode (Figures 1a, 1b). If the bus is 32 bits wide, the HDMP-1032A/1034A chipset is capable of sending this data word as two separate word segments with the use of an external mux and demux as shown in Figure 1c. In this mode, the transmitter and receiver use the FLAG bit to indicate the first or second word segment. The HDMP-1032A/ 1034A chipset may also be configured in full duplex to achieve a 32 bit wide bus extension. In addition, 32 bit wide data can be transmitted over two parallel serial lines as shown in Figure 1d. Low latency bus extension of a 16 bit wide data bus may be achieved using the full duplex configuration (Figure 1e). In this mode, link startup is achieved by exchange of control words.
Rx
RXCLK0/1 REFCLK
Rx
RXCLK0/1 REFCLK
B) 16 BIT BROADCAST TRANSMISSION
HDMP-1022 fig 1b
MUX TXCLK
Tx
Rx
RXCLK0/1 REFCLK
DEMUX
C) 32 BIT SIMPLEX TRANSMISSION
HDMP-1022 fig 1c
Tx TXCLK Rx RXCLK0/1 REFCLK
Tx TXCLK
Rx
RXCLK0/1 REFCLK
D) 32 BIT SIMPLEX TRANSMISSION
HDMP-1022 fig 1d
Tx TXCLK Rx RXCLK0/1 REFCLK
RXCLK0/1 REFCLK
Rx
Tx TXCLK
E) 16 BIT DUPLEX TRANSMISSION
Figure 1. Various configurations using the HDMP-1032A/1034A.
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Setting the Operating Data Rate Range The HDMP-1032A/1034A chipset can operate from 260 MBaud to 1400 MBaud. It is divided into three operating data ranges with each range selected by setting DIV1/0 as shown in the Typical Operating Rates table. Two examples have been provided in order to help in understanding and using this table. Example 1 (Unique Range) It is desired to transmit a 16 bit parallel word operating at a frequency of 60 MHz (60 MWord/ sec). Both the Tx and Rx must be set to a range that covers this word rate. According to the table only a setting of DIV1/0 = (0/0) allows a parallel input word rate of 40 to 70 MHz. This range setting easily accommodates the required 60 MHz word rate and
is unique. The user serial data rate is calculated as: Serial Data Rate =
60MW 16bits (-----) (-----) = Word sec
960 MBits/sec The baud rate includes an additional four encoding bits (20 bits total) that the HDMP-1032A/34A G-Link chipset transmits. The serial baud rate is calculated as: Serial Baud Rate =
60MW 20bits (-----) (-----) = Word sec
setting of DIV1/0 = (0/1) gives an upper rate of 45 MHz while a setting of DIV1/0 = (0/0) gives a lower rate of 40 MHz. The upper and lower data rates stated in the tables are typical values unless indicated by (min) or (max) and may vary between individual parts. However, each transmitter/receiver has overlapping ranges of operation providing continuous band coverage from 260 to 1400 MBaud. In this example, each transmitter/ receiver will permit a 42.5 MHz parallel data rate but it is suggested that DIV0 be tied to a jumper that can be set either to logic `1' (open allowing DIV0 to float high) or logic `0' (ground). This allows the design to accommodate both ranges for maximum flexibility. This technique is recommended whenever operating near the upper and lower ends of two adjacent word rate ranges.
1200 MBaud Example 2 (Overlapping Ranges) Some applications may have a parallel word rate that seems to fit in two ranges of operation. For example, a 42.5 MHz (42.5 MWord/s) parallel data rate falls within two ranges: DIV1/0 = (0/0) and DIV1/0 = (0/1). According to the table, a
HDMP-1032A (Tx), HDMP-1034A (Rx) Typical Operating Rates1,2 Tc = -20C to +85C, VCC = 3.15V to 3.45V Parallel Word Rate (MWord/sec) DIV1 0 0 1 DIV0 0 1 40 20 Range 70 (max) 45 640 320 Serial Data Rate (MBits/sec) Range 1120 (max) 720 800 400 Serial Baud Rate (MBaud) Range 1400 (max) 900
Figure 2. Typical data rates showing ranges of operation1.
Notes: 1. All values in this table and graph are typical unless otherwise noted by (min) or (max), (min) indicates a minimum guaranteed value, (max) indicates a maximum guaranteed value. 2. All values in this table are expected for a BER less than 10-14. 4
;;;; ;;; ;;;; ;; ;;
0 13 (min) 26 208 (min) 416
WORD RATE (MWords/sec) 50 5 25 75 0/0 0/1 1/0 800 400 900 260 (MIN.) 100 520 500 1000 1500 SERIAL BAUD RATE (MBaud)
260 (min) 520
100
DIV 1 / DIV 0
1400 (MAX.)
2000
HDMP-1032A Tx Block Diagram The HDMP-1032A transmitter was designed to accept 16 bit wide parallel words and transmit them over a high-speed serial line. The HDMP-1032A performs the following functions: * Latching parallel word input * Phase lock to TXCLK * High speed clock multiplication * Word encoding * Parallel to Serial Multiplexing PLL/Clock Generator The Phase Lock Loop and Clock Generator are responsible for generating all the internal clocks needed by the transmitter to perform its functions. These clocks are based on a supplied word clock (TXCLK) and control signals (TXDIV1/0, TCLKENB). TXCLK is the incoming word clock. The PLL/Clock Generator locks on to this incoming rate and multiplies the word rate clock by 20 (16 word bits + 4 encoding bits). As lock is achieved, LOCKED is set high. The TXDIV1/0 pins configure the transmitter to accept incoming data words within the desired frequency range.
ESMPXENB
By setting TCLKENB high, the user may provide an external TTL high speed serial clock at TXCLK. This clock replaces the internal VCO clock and is intended for diagnostic purposes only. This uncharacterized signal is used directly by the high-speed serial circuitry to output the serial data at speeds that are not within the VCO range. C-Field and W-Field Encoder Logic This logic determines what information is sent to the encoded word mux. If TXCNTL is high, the logic sends bits TX[0-13] and a C-Field (coding field) encoded as a control word regardless of the state of TXDATA. If TXCNTL is low and TXDATA is high, the logic sends TX[0-15] and a C-Field encoded as a data word. If neither TXCNTL nor TXDATA is set high, then the transmitter assumes the link is not being used. In this case, the logic submits an Idle Word to the encoded word mux to maintain the DC balance on the serial link and allow the receiver to maintain frequency and phase lock.
The C-Field logic, based on the inputs at TXCNTL, TXDATA, TXFLGENB and TXFLAG, supplies the four bits of the C-field to the encoded word mux. These bits contain information regarding the word type: Control, Data or Idle. In order for the TXFLAG bit to be used as an additional data bit, TXFLGENB must be set high on the Tx and RXFLGENB must be set high on the Rx. If scrambling of the encoding of the flag bit is desired, ESMPXENB pin must be set high on both the Tx and Rx. See Flag Descrambler section on next page for a more detailed description of the enhanced simplex mode. The W-Field logic (word field) presents either bits TX[0-15] or an Idle Word to the encoded word mux. Encoded Word Mux The Word Mux accepts the four encoding bits from the C-Field and 16 data bits from the W-Field. These 20 bits of parallel information are then multiplexed to a serial line based on the internal high-speed serial clock.
TXFLGENB
TXDIV1/0
TCLKENB
LOCKED
TXCLK
TXCAP0 TXFLAG FLAG ENCODER C-FIELD ENCODER PLL / CLOCK GENERATOR TXCAP1
TXDATA TXCNTL
LATCH INPUT
SIGN
INVERT
INPUT LATCH
TX[0-15]
W-FIELD ENCODER
WORD MUX
ACCUMULATE
HSOUT +
Figure 3. HDMP-1032A Transmitter Block Diagram.
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Sign The sign circuitry determines the disparity of the encoded word. Disparity is defined as the total number of high bits minus the total number of low bits. Accumulator Block This block is responsible for keeping track of total disparity of all previously sent words. Invert Block The Invert block is responsible for maintaining the DC balance of the serial line. It determines based on history and the sign of the current encoded word whether the current encoded word should be inverted to bring the serial line closer to the desired 50% duty cycle. HDMP-1034A Rx Block Diagram The HDMP-1034A receiver was designed to convert a serial data signal sent from the HDMP-1032A
RXDIV1/0 TSTCLK
into either 16 or 17 bit wide parallel data. The HDMP-1034A performs the following functions: * Frequency Lock * Phase Lock * Encoded Word Synchronization * De-multiplexing * Word Decoding * Encoding Error Detection Input Sampler and Clock-Data Recovery (CDR) In order to compensate for any amplitude distortion present in the serial data signal, the highspeed inputs, HSIN , are always equalized. The CDR block locks to the frequency of the REFCLK and to the phase of the sampled input signal. The recovered data is sent to the DEMUX block and a bit-rate clock is sent to the Clock Generator block. If the serial data signal is absent, the CDR block will maintain frequency lock onto REFCLK.
The RXDIV1/0 pins select the data rate range by dividing the VCO range by 1, 2 or 4. When RXDIV1/0 = 1/1, the internal VCO is bypassed and the test clock input TSTCLK can be used as the serial input. Clock Generator Using the recovered bit-rate clock, the CLOCK GENERATOR block generates all of the required internal clocks including the word rate clocks: RXCLK0/1. Using the WORD ALIGN block's bit adjust output, the phase of the word-rate clocks is adjusted bit by bit for proper word alignment. For testing purposes this adjustment function can be disabled using the WSYNCDSB input; word alignment can also be forced using the #RESET pin.
RXCAP1/0 PASS SYSTEM RX[0-15]
OUTPUT LATCH
HSIN + CDR REFCLK
INVERT DEMUX DECODE
DELAY
RXFLAG RXREADY RXERROR RXDATA RXCNTL RXDSLIP
CLOCK GENERATOR
WORD ALIGN FLAG DESCRM
SYNC LOGIC
SHFIN SHFOUT SRQIN SRQOUT PASSENB
WSYNCDSB
RXCLK0/1
Figure 4. HDMP-1034A Receiver Block Diagram.
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ESMPXENB
RXFLGENB
#RESET
Demultiplexer (DEMUX) This block takes the recovered serial data from the CDR block and demultiplexes it into a 20-bit parallel word comprised of a 16-bit word-field and 4-bit code-field. Decoder (DECODE) This block decodes the 4-bit code-field and determines whether the 16-bit word-field is: normal or inverted; data, control, or idle words; or errors. The flag bit is also decoded from the data word. Word Alignment (WORD ALIGN) This block detects the error output of the decoder block. Upon detecting two consecutive errors, WORD ALIGN requests a bit adjustment to the clock generator (assuming WSYNCDSB=0). If enhanced simplex mode is engaged (ESMPXENB=1), the Word Align block looks for a transition in the scrambled flag bit over a window of 32 words. If a transition is not detected, WORD ALIGN requests a bit adjustment to the clock generator (assuming WSYNCDSB=0). When the bit adjustment output has been low for 64 up to 128 words, the RXREADY output goes high. If the bit adjustment output goes high, RXREADY immediately goes low. Flag Descrambler (FLAG DESCRM) This block descrambles the flag bit if the enhanced simplex mode is engaged (ESMPXENB=1); otherwise, the flag bit is unaltered. Scrambling ensures that the flag bit is dynamic and thus can be detected by the word alignment block. Scrambling of the flag bit provides an extra level of protection to guard against improper word alignment caused by
static valid code-field bits being embedded within the data-field. Enhanced simplex mode can be turned off (ESMPXENB=0) to make it compatible with previous versions of G-Link. With this mode turned off and TXFLGENB=1, the flag bit is sent unscrambled to the Rx. If TXFLGENB=0, the flag bit will alternate at the Tx. When RXFLGENB=0, the Rx will use this alternating flag for error checking. Parallel Automatic Synchronization System (Pass) As shown in Figure 4, this system consists of three blocks: the parallel delay block (DELAY), the output latch block (OUTPUT LATCH), and the synchronization logic block (SYNC LOGIC). This system was designed to provide a simple interface to the parallel outputs for a synchronous system. Background Traditionally, the parallel outputs are clocked out with the falling edge of RXCLK1 as shown in Figure 4.1. Since this clock is recovered from the serial data, this clock is synchronous with the remote clock at the Tx.
When the Tx and Rx clock are not synchronous, FIFO's are usually used to cross the frequency domains. The size of the FIFO and the frequency difference determine the maximum packet size of transmission. When the clock from the Tx is synchronous with the Rx clock, data can be transmitted continuously without FIFO's since the parallel output data is synchronous with the local REFCLK. However, due to link distance and other physical variables, the relative phase of the REFCLK to the recovered data is unpredictable. Because of this unknown phase, the sampling of the recovered word must be adjusted so that the internal setup/hold times are not violated. Furthermore, in a multichannel system, the setting of the phase must be consistent so that time slots across the channels are preserved. The PASS system was designed to address these issues by sensing the phase difference between the local REFCLK with the recovered clock, and shifts the phase of the parallel output data with the DELAY block, such that it can be clocked out with the rising edge
NC
SRQIN
DATA 16 BITS
TX[0-15] HSOUT HSIN
SHFIN SHFOUT RXCLK0/1 RX[0-15]
NC NC
Tx
Rx
PASSENB
TXCLK
SRQOUT
REFCLK
TXCLK
NC
REFCLK
Figure 4.1. Traditional G-Link configuration with PASS disabled (PASSENB=0). Recovered data words and RXCLK0/1 are synchronous with TXCLK.
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of the REFCLK. By adjusting the phase of the data word rather than REFCLK, the optimal setup time is achieved for the input latches of the chip interfacing to the Rx. As the relative phase between the HSIN input and the REFCLK drift slowly over time due to environmental variations, the PASS system is able to absorb this to some degree, and is able to reset and re-optimize the sampling when the margin is exceeded. DELAY Block The parallel DELAY block has an adjustable delay range of 20% to 80% of the data word. Its delay is controlled by the SYNC LOGIC block. This delay block is used for all of the data bits, flag bit, as well as the status bits. OUTPUT LATCH Block This block is a bank of positive edge triggered D-flip/flops. The clock is selected by the SYNC LOGIC block to be either the recovered clock RXCLK1 when the PASS system is disabled, or the REFCLK when the PASS system is enabled (PASSENB=1). SYNC LOGIC Block The SYNC LOGIC block's function is to compare the phase of the recovered data to REFCLK, to set the state of the DELAY block, to detect when the DELAY range has been exceeded, and to recover with a new DELAY setting. It is also designed to support a master/slave configuration in a multi-channel environment.
When RXREADY goes high, the optimal delay choice is determined at the shift output SHFOUT: SHFOUT = 0 DELAY retract SHFOUT = 1 DELAY extend The actual setting of the DELAY block is determined with the shift input SHFIN. When the phase of the REFCLK drifts to within 10% of the word boundary, the RXDSLIP output is set high, and a new choice of SHFOUT is chosen. The shift request output SQROUT is set high when a RXDSLIP condition is detected, or if the shift request input SRQIN goes high.
Single Channel Configuration In a single channel configuration, SHFIN is simply tied to SHFOUT as shown in Figure 4.2. The daisy chaining signal SRQIN is set low (grounded) and SRQOUT is left unconnected. After RXREADY goes high, the DELAY block can absorb a phase variation between the serial input HSIN and the REFCLK a minimum of ideally 4 serial bits, or 20% of the word period. This margin is reduced due to finite rise/fall times and setup times of the internal circuitry.
SRQIN
DATA 16 BITS
TX[0-15] HSOUT HSIN
SHFIN SHFOUT RXCLK0/1 RX[0-15]
Tx
Rx
PASSENB
TXCLK +VCC
SRQOUT NC
REFCLK
REFCLK
Figure 4.2. Single channel configuration with PASS enabled (PASSENB=1). Recovered data words and RXCLK0/1 are synchronous with REFCLK.
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Multiple Channel Configuration The connections for a multiple channel configuration are shown in Figure 4.3. The daisy-chain signals SRQIN and SRQOUT are used to allow each receiver's PASS system shift requests to propagate to the master, which is the last of the chain. The master then controls the shift command SHFOUT, which is tied common to the SHFIN of each receiver. The first
SRQIN in the chain is grounded; the SRQOUT of the master as well as the SHFOUT outputs of the slave units are left unconnected. When the internal parallel data boundary of the master, or any of the slaves come within 10% of the REFCLK, the RXDSLIP output is set high by the respective Rx,
a shift request (SRQOUT=1) is issued which propagates to the master. The master again selects an optimum SHFOUT, which sets the DELAY blocks of all receivers consistently. The phase absorption margin for a multiple channel configuration is the same as the single channel case, less the channel-to-channel skews.
SRQIN
DATA 16 BITS
TX[0-15] HSOUT- HSIN-
SHFIN SHFOUT RXCLK0/1 RX[0-15]
NC
Tx
Rx (SLAVE)
PASSENB SRQOUT +VCC REFCLK
TXCLK
SRQIN
DATA 16 BITS
TX[0-15] HSOUT- HSIN-
SHFIN SHFOUT RXCLK0/1 RX[0-15]
NC
Tx
Rx (SLAVE)
PASSENB SRQOUT +VCC REFCLK
TXCLK
SRQIN
DATA 16 BITS
TX[0-15] HSOUT- HSIN-
SHFIN SHFOUT RXCLK0/1 RX[0-15]
Tx
Rx (MASTER)
PASSENB SRQOUT +VCC NC REFCLK REFCLK
TXCLK
Figure 4.3. Multiple channel configuration with PASS Enabled (PASSENB=1).
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HDMP-1032A (Tx) Timing The Tx timing diagram is shown in Figure 5. Under normal operations, the Tx PLL locks an internally generated clock to the incoming TXCLK at which time LOCKED is set high. The incoming data, TX[0-15], TXDATA, TXCNTL, and TXFLAG are latched by this internal clock. The data must be valid for ts before it is sampled and remain valid for a time th after it is sampled.
The setup and hold time parameters, ts and th, are referenced to the rising edge of TXCLK. The start of a word, bit TX[0], in the high speed serial output occurs after a delay of td after the rising edge of the TXCLK. The typical value of td is approximately one clock cycle.
HDMP-1032A (Tx) Timing Characteristics Tc = -20C to +85C, VCC = 3.15V to 3.45V Symbol ts th Parameter Setup Time, for TX[0-15], TXDATA, TXCNTL and TXFLAG Relative to Rising Edge of TXCLK. Hold Time, for TX[0-15], TXDATA, TXCNTL and TXFLAG Relative to Rising Edge of TXCLK. Unit nsec nsec Min. 2.5 2.5 Typ. Max.
TXCLK
TX[0-15] TXDATA TXCNTL TXFLAG ts th
HSOUT W-FIELD td C-FIELD
Figure 5. HDMP-1032A (Tx) Timing Diagram.
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HDMP-1034A (Rx) Timing The Rx timing diagram when RXREADY=1 is shown in Figure 6. The serial data stream is deserialized into a parallel word at 1/20 the serial baud rate. When the PASS system is disabled (PASSENB=0), there is a latency delay of two words from the input of the first serial bit of a word to the parallel outputs. The parallel outputs, RX[0-15], RXFLAG, RXREADY, RXERROR,
RXDATA, RXCNTL and RXDSLIP are clocked out with the falling edge of RXCLK1 and appear after a delay of td. RXCLK1 and its complement RXCLK0 are both 50% duty cycle clocks. When the PASS system is enabled (PASSENB=1), the timing of the parallel word is adjusted automatically 30% of the word period so that it can be clocked out with the rising edge of REFCLK and appear after a delay of tdp.
HDMP-1034A (Rx) Timing Characteristics Tc = -20C to +85C, VCC = 3.15V to 3.45V. Typical values are at Tc = 25C, VCC = 3.3V Symbol td tdp tsk Parameter Synchronous Output Delay referenced to the falling edge of RXCLK1, PASS System Disabled (PASSENB=0). Synchronous Output Delay referenced to the rising edge of REFCLK, PASS System Enabled (PASSENB=1). Allowable skew between HSIN and REFCLK before PASS system resets, PASSENB=1. Unit nsec nsec nsec Min. 0 6.0 Typ. 2.0 6.6 Max. 3.5 8.0 20% word period -0.4 nsec
WORD 1 W BIT 0 HSIN
C
WORD 2 W
C
WORD 3 W
C
WORD 4 W
C
RXCLK1
RXCLK0
REFCLK
RX[0] td tdp
NOTE: W = 16 BIT WORD FIELD, C = 4 BIT CODE FIELD
Figure 6. HDMP-1034A (Rx) Timing Diagram.
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HDMP-1032A (Tx), HDMP-1034A (Rx) DC Electrical Specifications Tc = -20C to +85C, VCC = 3.15V to 3.45V, Typical values are at Tc = 25C, VCC = 3.3V Symbol VIH,TTL VIL,TTL VOH,TTL VOL,TTL IIH,TTL IIL,TTL VIP,H50 VOP,BLL ICC,Tx ICC,Rx Parameter TTL Input High Voltage Level, Guaranteed high signal for all inputs. TTL Input Low Voltage Level, Guaranteed low signal for all inputs. TTL Output High Voltage Level, IOH = -400 A TTL Output Low Voltage Level, IOL = 500 A Input High Current, VIN = VCC Input Low Current, VIN = 0 volts H50 Input Peak-To-Peak Differential Voltage BLL Output Peak-To-Peak Differential Voltage, Terminated with 50 , ac coupled Transmitter VCC Supply Current Receiver VCC Supply Current Unit V V V V A A mV mV mA mA 200 1000 200 240 Min. 2.0 0 2.2 0 Typ. Max. VCC 0.8 VCC 0.6 40 600
AC Electrical Specifications Tc = 25C Symbol tr,TTL in tf,TTL in tr,TTL out tf,TTL out tr,BLL tf,BLL VSWRi,H50 VSWRo,BLL tfa tRx_wa Parameter Input TTL Rise Time, 0.8 to 2.0 volts Input TTL Fall Time, 2.0 to 0.8 volts Output TTL Rise time, 0.8 to 2.0 volts, 10 pF load Output TTL Fall Time, 2.0 to 0.8 volts, 10 pF load BLL Rise Time, Terminated with 50, ac coupled1 BLL Fall Time, Terminated with 50, ac coupled1 H50 Input VSWR BLL Output VSWR Transmitter & Receiver Frequency Acquisition Time at Power-on2 Receiver Word Alignment Time msec Words Unit nsec nsec nsec nsec psec psec 240 240 2:1 2:1 4 300 Min. Typ. 2 2 3.0 3.0 Max.
Notes 1. Rise and fall times are measured between 20% and 80% of the voltage range. 2. Frequency acquisition time is independent of DIV1/DIV0 data rate range.
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Latency Tc = 25C Latency (Word Clock Cycles) PASSENB = 0 Tx Rx 1.4 2.6 PASSENB = 1 1.4 3.0 Delay from the rising edge of TXCLK to the first bit TX[0] in the serial stream Delay from the first bit RX[0] in the serial stream to the falling edge of RXCLK1 (or the rising edge of REFCLK if the PASS system is enabled, PASSENB=1) Latency Definition
Link
4.0
4.4
Transmit Word Clock (TXCLK) and Receiver Reference Clock (REFCLK) Requirements Tc = -20C to +85C, VCC = 3.15 V to 3.45 V Symbol Ftol Symm Parameter TXCLK and REFCLK Frequency Tolerance (REFCLK is referenced to TXCLK) Symmetry (Duty Cycle) Unit ppm % Min. -100 40 Typ. Max. +100 60
HDMP-1032A (Tx), HDMP-1034A (Rx) Absolute Maximum Ratings TA = 25C except as specified. Operation in excess of any one of these conditions may result in permanent damage to the device. Symbol VCC VIN,TTL VIN,BLL IO,TTL Tstg TJ Tmax Parameter Supply Voltage TTL Input Voltage H50 Input Voltage TTL Output Source Current Storage Temperature Junction Temperature Maximum Assembly Temperature (10 seconds maximum) Unit V V V mA C C C -65 0 Min. -0.5 -0.7 2.0 Max. 5.0 5.5 VCC 13 +150 +150 +260
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HDMP-1032A (Tx) Thermal Characteristics TA = 25C Symbol jc1 PD Parameter Thermal Resistance, Die to Case Power Dissipation, VCC = 3.3 V Unit C/W mW Typ. 8 660
HDMP-1034A (Rx) Thermal Characteristics TA = 25C Symbol jc1 PD Parameter Thermal Resistance, Die to Case Power Dissipation, VCC = 3.3 V Unit C/W mW Typ. 8 792
I/O Type Definitions I/O Type I-TTL O-TTL HS_OUT HS IN C S Definition Input TTL. Floats high when left open. Output TTL 50 Matched Output Driver. Will drive AC coupled 50 loads. All unused outputs should be AC coupled to a 50 resistor to ground. High Speed Input Filter Capacitor Node Power Supply or Ground
Note: 1. Based on independent package testing by HP. ja for the HDMP-1032A and HDMP-1034A is 50C/W. ja is measured on a standard 3" x 3" two layer PCB in a still air environment. In order to determine the actual junction temperature in a given application, use the following formula: TJ = TC + (jc x PD), where TC is the case temperature measured on the top center of the package and PD is the power being dissipated.
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64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VCC TX[13] TX[12] TX[11] TX[10] TX[9] TX[8] VCC_A2 GND_A2 TX[7] TX[6] TX[5] TX[4] TX[3] TX[2] VCC
GND 1 TX[14] 2 TX[15] 3 TXCNTL 4 TXDATA 5 TXFLAG 6 NC 7 VCC_TTL 8 GND_TTL 9 TXFLGENB 10 ESMPXENB 11 LOCKED 12 VCC 13 GND 14 NC 15 NC 16
A HDMP-1032A LOT# Tx DATE CODE
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
GND TX[1] TX[0] NC NC NC NC VCC_TTL GND_TTL NC NC TXCLK VCC GND NC TXCAP1
Figure 7. HDMP-1032A (Tx) Package Layout, Top View.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VCC_TTL RX[2] RX[3] RX[4] RX[5] RX[6] RX[7] VCC_TTL GND RX[8] RX[9] RX[10] RX[11] RX[12] RX[13] VCC_TTL
VCC_HS 17 GND_HS 18 HSOUT-- 19 HSOUT+ 20 NC 21 NC 22 NC 23 VCC 24 GND 25 TXDIV0 26 TXDIV1 27 TCLKENB 28 NC 29 GND_A1 30 VCC_A1 31 TXCAP0 32
GND_TTL 1 RX[1] 2 RX[0] 3 RXREADY 4 RXERROR 5 RXDSLIP 6 VCC_TTL 7 GND_TTL 8 VCC 9 GND 10 REFCLK 11 TSTCLK 12 SHFIN 13 SHFOUT 14 SRQOUT 15 VCC_HS 16
A HDMP-1034A LOT# Rx DATE CODE
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
GND_TTL RX[14] RX[15] RXFLAG RXDATA RXCNTL VCC_TTL GND_TTL VCC GND RXCLK1 RXCLK0 WSYNCDSB #RESET SRQIN RXCAP1
Figure 8. HDMP-1034A (Rx) Package Layout, Top View.
15
GND_HS 17 HSIN+ 18 HSIN-- 19 GND_HS 20 NC 21 RXFLGENB 22 ESMPXENB 23 VCC 24 GND 25 PASSENB 26 NC 27 RXDIV0 28 RXDIV1 29 VCC_A 30 GND_A 31 RXCAP0 32
HDMP-1032A (Tx) Pin Definition User Mode Options Name TXFLGENB Pin 10 Type I-TTL Signal Flag Bit Mode Select: When this input is high, the TXFLAG bit input is sent as an extra 17th data bit during data word transfers. As an example, the flag bit can be used as an even or odd word indicator for 32 bit transmission. The RXFLGENB input on the Rx chip must be set to the same value as the TXFLGENB pin. Enhanced Simplex Mode Enable: Enables scrambling of the Flag Bit encoding. The ESMPXENB pin on the Rx chip must be set to the same value. This mode should be enabled unless compatibility with previous versions of G-Link (i.e. HDMP-1024/1014) is desired desired which don't have this feature. Transmit Data Word: This input tells the chip that the user has valid data to be transmitted. When this pin is asserted and TXCNTL is low, bits TX[0-15] and optionally TXFLAG are encoded and sent as a data word. Transmit Control Word: This input tells the Tx chip that the user is requesting a control word to be transmitted. When this pin is asserted, bits TX[0-13] are sent as a control word. If TXCNTL and TXDATA are asserted simultaneously, TXCNTL takes precedence. Idle words are transmitted if both TXDATA and TXCNTL are low. Serial Data Output: These pins form a buffer line logic driver, which is a 50 terminated PECL compatible output. Word Inputs: When sending data words, TX[0-15] are serialized. When sending control words, TX[0-13] are serialized.
ESMPXENB
11
I-TTL
TXDATA
5
I-TTL
TXCNTL
4
I-TTL
High-Speed Serial/Parallel I/O HSOUT+ HSOUTTX[0] TX[1] TX[2] TX[3] TX[4] TX[5] TX[6] TX[7] TX[8] TX[9] TX[10] TX[11] TX[12] TX[13] TX[14] TX[15] TXFLAG 20 19 46 47 50 51 52 53 54 55 58 59 60 61 62 63 2 3 6 HS_OUT I-TTL
I-TTL
Flag Bit: When TXFLGENB is active, this input is sent as an extra data bit in addition to the 16 data word bits. When TXFLGENB is not asserted, this input is ignored and an alternating internal flag bit is transmitted to allow the Rx chip to perform error detection during data word transfers. The Flag Bit is not sent when a control word is transmitted.
16
HDMP-1032A (Tx) Pin Definition (continued) PLL/Clock Generator Name TXCAP0 TXCAP1 TXCLK Pin 32 33 37 Type C Signal Loop Filter Capacitor: A 0.1 F min. loop filter capacitor, C2, must be connected across TXCAP0 and TXCAP1 for all combinations of TXDIV1/TXDIV0. See Figure 12. Transmit Word Clock Input: When TCLKENB is low, this word rate clock input is phase locked and multiplied to generate the highspeed serial clock. When TCLKENB is high, the PLL is bypassed and TXCLK becomes the serial clock. VCO Divider Select: These pins program the VCO divider chain to operate at full, half or quarter speed. See Typical Operating Rates table and Figure 2. Locked to TXCLK: This pin goes high when the transmit PLL achieves frequency lock to the TXCLK signal. Logic Power Supply: Normally 3.3 volts. This power supply is used for the internal transmitter logic.
I-TTL
TXDIV0 TXDIV1 LOCKED
26 27 12
I-TTL
O-TTL
Power Supply/Ground VCC 13 24 36 49 64 8 41 17 31 57 1 14 25 35 48 9 40 18 30 56 28 S
VCC_TTL VCC_HS VCC_A1 VCC_A2 GND
S S S S
TTL Power Supply: Normally 3.3 volts. Used for all TTL transmitter input and output buffer cells. Serial Output Power Supply: Normally 3.3 volts. Used for Serial Output pins. Analog Power Supply: Normally 3.3 volts. Used for the analog section. Ground: Normally 0 volts. Tie to ground.
GND_TTL GND_HS GND_A1 GND_A2 TCLKENB
S S S
TTL Ground: Normally 0 volts. Tie to ground. Serial Output Ground: Normally 0 volts. Analog Ground: Normally 0 volts.
Test Mode/No Connect Pins I-TTL Enable External Serial Rate Clock Input: When set high, this input causes the TXCLK input to be used for the serial transmit clock rather than the internal VCO clock. It is intended for diagnostic purposes and normally tied low. No Connect: These pins should be left unconnected.
NC
7 15 16 21 22 23 29 34 38 39 42 43 44 45
17
HDMP-1034A (Rx) Pin Definition User Mode Options/Status Name RXFLGENB ESMPXENB Pin 22 23 Type I-TTL I-TTL Signal Flag Bit Mode Select: When set high, the RXFLAG bit output is available to the user as an extra 17th data bit. Enhanced Simplex Mode Enable: Enables descrambling of the Flag Bit encoding. The ESMPXENB pin on the Tx chip must be set to the same value. This mode should be enabled unless compatibility with previous versions of G-Link (i.e. HDMP-1022/1012) is desired which don't have this feature. Enable Parallel Automatic Synchronization System: The parallel Rx data and control words are read out with REFCLK instead of the incoming word's parallel clock. The relative phase of the parallel output bits is internally adjusted so that they are clocked out with the rising edge of the REFCLK. Data Word Available Output: This output indicates that the Rx chip word outputs RX[0-15] have a data word. Control Word Available Output: This output indicates that the Rx chip word outputs RX[0-13] have a control word. Serial Data Input Word Outputs
PASSENB
26
I-TTL
RXDATA RXCNTL
44 43
O-TTL O-TTL
High-Speed Serial/Parallel I/O HSIN+ HSINRX[0] RX[1] RX[2] RX[3] RX[4] RX[5] RX[6] RX[7] RX[8] RX[9] RX[10] RX[11] RX[12] RX[13] RX[14] RX[15] RXFLAG 18 19 3 2 63 62 61 60 59 58 55 54 53 52 51 50 47 46 45 HS_IN O-TTL
O-TTL
Flag Bit: If both TXFLGENB and RXFLGENB have been asserted, this output indicates the value of the transmitted flag bit which can be used as an extra 17th data bit. Receiver Ready: This signal is asserted when the word alignment block has seen error-free code field nibbles for 64 up to 128 consecutive words. When ESMPXENB = 1, the toggling of the scrambled flag bit is also checked. RXREADY is de-asserted upon 2 consecutive errors in the code field or if the toggling of the flag bit is absent when ESMPXENB=1. Received Data Error: Asserted when a word is received which does not correspond to either a valid Data, Control, or Idle Word encoding.
Link Status RXREADY 4 O-TTL
RXERROR
5
O-TTL
18
HDMP-1034A (Rx) Pin Definition (continued) CDR/Clock Generator Name RXCAP0 RXCAP1 REFCLK Pin 32 33 11 Type C Signal Loop Filter Capacitor: A 0.1 F min. loop filter capacitor, C2, must be connected across RXCAP0 and RXCAP1 for all combinations of RXDIV1/RXDIV0. See Figure 12. Reference Clock Input: The Rx PLL uses this input for frequency lock. In addition, RX[0-15], RXFLAG, RXDATA, RXCNTL, RXREADY, RXERROR, and RXDSLIP are clocked out on the rising edge of REFCLK when PASSENB=1. VCO Divider Select: These pins program the VCO divider chain to operate at full, half, or quarter speed. See Typical Operating Rates table and Figure 2. Recovered Word-Rate Clock Outputs: These outputs are the PLL recovered word rate clocks. RX[0-15], RXFLAG, RXDATA, RXCNTL, RXREADY, RXERROR, and RXDSLIP are clocked out on the falling edge of RXCLK1 when PASSENB=0. RXCLK0 is the inverse of RXCLK1. Power Supply: Normally 3.3 volts. This power supply is used for all the core logic other than the output drivers. TTL Power Supply: Normally 3.3 volts. Used for all TTL receiver input and output buffer cells.
I-TTL
RXDIV0 RXDIV1 RXCLK0 RXCLK1
28 29 37 38
I-TTL
O-TTL
Power Supply/Ground VCC 9 24 40 7 42 49 57 64 16 S
VCC_TTL
S
VCC_HS
S
High-Speed Supply: Normally 3.3 volts. This supply is used to provide clean references for the high-speed inputs, HSIN+ and HSIN-. Analog Power Supply: Normally 3.3 volts. This supply is used to feed power to the analog section of the chip. Ground: Normally 0 volts. Tie to ground.
VCC_A GND
30 10 25 39 56 1 8 41 48 17 20
S S
GND_TTL
S
TTL Ground: Normally 0 volts. Tie to ground.
GND_HS
S
High-Speed Input Ground: When tied to ground, the input impedance of HSIN+ and HSIN- are each matched to 50 . In order to obtain high impedance (high-Z) inputs for 1:N broadcast applications, 18 K series resistors to -5 V are recommended. Analog Ground: Normally 0 volts. This ground is used for the analog PLL portion of the chip.
GND_A
31
S
19
HDMP-1034A (Rx) Pin Definition (continued) Pass System RXDSLIP 6 O-TTL Rx Word Slip: This output is asserted whenever the phase of the parallel word relative to the reference clock has exceeded the range of the internal delay, which results in a slippage of one word. See discussion of PASS system on page 7. Shift Input: This input controls the delay of the parallel bits to be clocked out by REFCLK when PASSENB=1. In a single Rx configuration, SHFIN is connected to SHFOUT. In a multiple Rx configuration, all SHFIN are connected to the master's SHFOUT. Shift Output: This output, normally connected to SHFIN, is generated based on the relative phase between REFCLK and the internal parallel output bits. Shift Request Input: In a daisy chain configuration, this input allows a shift request to be propagated to the master. SRQIN is connected to the SRQOUT of the previous Rx in a multi-receiver configuration. Shift Request Output: In a daisy chain configuration, this output is connected to the SRQIN input of the next receiver. SRQOUT goes high when a SRQIN=1 or when the relative phase between the REFCLK and the internal parallel bits requires a shift. External Serial Rate Clock Input: When RXDIV1/0 = 1/1, this input is used in place of the normal VCO signal, effectively disabling the PLL and allowing the user to provide an external serial clock for testing. Pin is normally tied to VCC_TTL. Reset: When this active low input is asserted the word alignment is reset. Upon release (low to high) the normal word alignment process is reinstated. Pin used for test purposes and is normally tied to VCC_TTL. Word Sync Disable: When high, disables resynchronization to word edge upon errors encountered in the C-field of the incoming encoded word. Pin used for test purposes and is normally tied low. No Connect: These pins should be left unconnected.
SHFIN
13
I-TTL
SHFOUT
14
O-TTL
SRQIN
34
I-TTL
SRQOUT
15
O-TTL
Test Mode/No Connect Pins TSTCLK 12 I-TTL
#RESET
35
I-TTL
WSYNCDSB
36
I-TTL
NC
21 27
20
Package Information Item Package Material Lead Finish Material Lead Finish Thickness Lead Skew Lead Coplanarity (seating plane method) Details Plastic 85% Tin, 15% Lead 300-800 m 0.20 mm max 0.10 mm max
Mechanical Dimensions
PIN #1 ID
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 47 3 46 4 45 5 44 6 43 7 42 HDMP-103xA 8 41 9 40 TOP VIEW 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
E1
E
c b D1 e D A2 L
G
A
A1
Mechanical Dimensions of HDMP-1032A/34A Dimensional Parameter (in millmeters) HDMP-103xA Tolerance D1/E1 14.00 0.10 D/E 17.20 0.25 b 0.35 0.05 e 0.80 Basic L 0.88 +0.15/ -0.10 c 0.17 Max G 0.25 Gage Plane A2 2.00 +0.10/ -0.05 A1 0.25 Max A 2.35 Max
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Appendix: Internal Architecture Information
Line Code Description The HDMP-1032A/1034A line code is Conditional Invert Master Transition (CIMT) as illustrated in Figure 9. The CIMT line code uses three types of words: Data words, Control words, and Idle words. Idle words are generated internally by the Tx when both TXDATA and TXCNTL are low. Each word consists of a Word Field (W-Field) followed by a Coding Field (C-Field). The C-Field has a master transition. Users can send arbitrary information carried by Data or Control Words. The DC balance of the line code is enforced automatically by the Tx. Idle words have a single rising edge at the master transition when operating in non-enhanced simplex mode. The coding definitions are summarized in the table on the next page. Note that the leftmost bit in each table is the first bit to be transmitted in time, while the rightmost bit is the last bit to be transmitted. Data Word Codes In Data Word mode, all 16 bits of the Tx are transmitted to the Rx, along with a flag bit. If TXFLGENB=1, then the user controls this bit with TXFLAG; otherwise it is internally set to alternate. Control Word Codes In Control Word mode, 14 bits are transmitted to the Rx. The lower 7 bits X0-X6 are sent in the w0-w6 space, and the upper 7 bits X7-X13 are sent in the w9-w15 space. Bits w7 and w8 are forced 01 for true, and 10 for inverted control words. The shifting of the word field is for backward compatibility with previous versions of G-Links chip sets. Idle Word and Error Codes Two Idle Words, IW1a and IW1b are provided. Unused word codes are mapped into Error States. Enhanced Simplex Mode In this mode (ESMPXENB=1), the flag bit is scrambled at the Tx and descrambled at the Rx. Since the Rx uses the scrambled flag bit for frame alignment, it is also defined for Control and Idle Words. However, the flag bit is only available to the user in the Data Word mode. The first bit w0 is also scrambled to aid word alignment.
WORD FIELD 16 BITS SERIAL BIT STREAM
CODING FIELD 4 BITS
MASTER TRANSITION
MASTER TRANSITION
IDLE WORD
WORD K
WORD K+1
Figure 9. HDMP-1032A/1034A (Tx/Rx Pair) Line Code.
22
Coding1 with ESMPXENB=0 (Compatible with previous G-Link chips, HDMP-1012/14, HDMP-1022/24) Word Type Flag W-Field w0 w1 w2 w3 w4 w5 w6 w7 w8 w9 Data Word Structure Data = True 0 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 Data = Inverted 0 #(X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 Data = True 1 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 Data = Inverted 1 #(X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 Control Word Structure Control = True X0 X1 X2 X3 X4 X5 X6 0 1 X7 Control = Inverted #(X0 X1 X2 X3 X4 X5 X6) 1 0 #(X7 Idle Word Structure Idle Word 1a 1111111110 Idle Word 1b 1111111000 Detectable Error States dddddddddd dddddddddd ddddddd0dd ddddddd11d dddddddddd dddddddddd Coding1 with ESMPXENB=1 Word Type Flag2 W-Field w03 w1 w2 Data Word Structure Data = True 0 X0 X1 X2 Data = Inverted 0 #(X0 X1 X2 Data = True 1 X0 X1 X2 Data = Inverted 1 #(X0 X1 X2 Control Word Structure Control = True 0 X0 X1 X2 Control = Inverted 0 #(X0 X1 X2 Control = True 1 X0 X1 X2 Control = Inverted 1 #(X0 X1 X2 Idle Word Structure Idle Word 1a 0 111 Idle Word 1b 0 111 Idle Word 1a 1 111 Idle Word 1b 1 111 Detectable Error States ddd ddd ddd ddd
C-Field w10 w11 w12 w13 w14 w15 c0 c1 c2 X10 X10 X10 X10 X11 x11 X11 x11 X12 X12 X12 X12 X13 X13 X13 X13 X14 X14 X14 X14 X15 X15) X15 X15) 1 0 1 0 1 0 0 1 0 1 0 0 0 1 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 0 1 0
c3 1 0 1 0 1 0 1 1 d d 0 0 0 1
X8 X9 X10 X11 X12 X13 0 X8 X9 X10 X11 X12 X13) 1 0 0 d d d d d d 0 0 d d d d d d 0 0 d d d d d d 0 0 d d d d d d 0 0 d d d d d d 0 0 d d d d d d 0 0 d d 1 1 1 0
C-Field w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 w14 w15 c0 c1 c2 X3 X3 X3 X3 X3 X3 X3 X3 1 1 1 1 d d d d X4 X4 X4 X4 X4 X4 X4 X4 1 1 1 1 d d d d X5 X5 X5 X5 X5 X5 X5 X5 1 1 1 1 d d d d X6 X6 X6 X6 X6 X6) X6 X6) 1 1 1 1 d d d d X7 X7 X7 X7 0 1 0 1 1 0 1 0 d d 0 1 X8 X8 X8 X8 X9 X9 X9 X9 X10 X10 X10 X10 X11 x11 X11 x11 X12 X12 X12 X12 X10 X10 X10 X10 0 0 0 0 d d d d X13 X13 X13 X13 X11 X11 X11 X11 0 0 0 0 d d d d X14 X14 X14 X14 X12 X12 X12 X12 0 0 0 0 d d d d X15 X15) X15 X15) X13 X13) X13 X13) 0 0 0 0 d d d d 1 0 1 0 0 1 0 1 0 0 0 0 d d 1 1 1 0 0 1 0 1 1 0 0 0 1 1 0 1 1 1 0 1 1 0 1 0 0 1 1 1 0 0 0 1 0 0
c3 1 0 1 0 1 0 1 0 1 1 1 1 d d 0 0
1 X7 X8 X9 0 #(X7 X8 X9 1 X7 X8 X9 0 #(X7 X8 X9 1 0 1 0 d d d 1 0 0 0 0 d d d d 0 0 0 0 d d d d 0 0 0 0 d d d d
Notes: 1. Xi denotes Txi or Rxi pin, # indicates Inversion, d denotes Don't Care cases. 2. Flag bit is scrambled prior to sending. It is only available to the user in Data Word mode. 3. w0 is scrambled during transmission to further enhance word alignment.
23
Tx Operation Principles The HDMP-1032A (Tx) is implemented monolithically in a high performance 25 GHz ft silicon bipolar process. The Tx performs the following functions for link operation: * Latching Parallel Word Input * Phase Lock to TXCLK * High-Speed Clock Multiplication * Word Encoding * Parallel to Serial Multiplexing In normal operation, the Tx phase locks to a user supplied word rate clock and multiplies the frequency to produce the high-speed serial clock. The Tx can accept either 16 or 17 bit wide parallel data and produce a 20 bit encoded word. Similarly, 14 bit control words can be transmitted in a 20 bit encoded word. Tx Encoding A simplified block diagram of the transmitter is shown in Figure 3. The PLL/Clock Generator locks onto the incoming word rate clock and multiplies it up to the serial clock rate. It also generates
all the internal clock signals required by the Tx chip. The data inputs, TX[0-15], as well as the control signals; TXDATA, TXCNTL and TXFLAG are latched in on the rising edge of an internally generated word rate clock. The word field is then encoded depending on the state of the TXDATA and TXCNTL signals. At the same time, the coding field is generated. At this point, the entire word has been constructed in parallel form and its sign is determined. This word sign is compared with the accumulated sign of previously transmitted bits to decide whether to invert the word. If the sign of the current word is the same as the sign of the previously transmitted bits, then the word is inverted. If the signs are opposite, the word is not inverted. No inversion is performed if the word is an idle word. The Word Field and Coding Field are encoded depending on TXDATA, TXCNTL, TXFLAG, TXFLGENB as well as two internally generated signals, O/E and ACCMSB.
When TXFLGENB is high and ESMPXENB is low, O/E is equivalent to TXFLAG. This is equivalent to adding an additional bit to the data field. When TXFLGENB is also low, O/E alternates between high and low for data words. This allows the link to perform more extensive error detection when the extra bit is unused. ACCMSB is the sign of the previously transmitted data. This is used to determine which type of Idle Word should be sent. When ACCMSB is low, IW1a is sent and when ACCMSB is high, IW1b is sent. This effectively drives the accumulated offset of transmitted bits back toward the balanced state. Tx Phase-Lock Loop The block diagram of the transmitter phase-lock loop (PLL) is shown in Figure 10. It consists of a sequential frequency detector, loop filter, VCO, clock generation circuitry and a lock indicator. The outputs of the frequency detector pass through a charge pump filter that controls the center frequency of the VCO.
EXTERNAL CAP
TXCLK
FREQUENCY DETECTOR
LOOP FILTER
VCO
INTERNAL CLOCKS
CLOCK GENERATOR
0 DIVIDE BY N 1 TXCLK
LOCK DETECT
TSTCLKEN TXDIV1/0
Figure 10. HDMP-1032A (Tx) Phase-Lock Loop.
24
An external serial clock can be used instead of the VCO clock. This is accomplished by setting TCLKENB high and applying a serial rate clock to TXCLK. Note that this mode is used for diagnostic purposes only. One of three frequency bands may be selected by applying the appropriate values to TXDIV1/0. The VCO or TXCLK frequency is divided by N where N is 1, 2, or 4 based on the settings of TXDIV1/0 as shown in the table below. This divided version of the VCO clock or TXCLK is used as the serial rate clock. N 1 2 4 TXDIV1 0 0 1 TXDIV0 0 1 X
* Word Decoding * Error Detection * Automatic Parallel Word Phase Adjustment Rx Data Path Figure 4 shows a simplified block diagram of the receiver. The data path consists of an Input Sampler, a Word Demultiplexer, a Coding Field (C-Field) Decoder, and a Word Field (W-Field) Decoder. An on-chip phase-lock loop (PLL) is used to extract timing reference from the serial input (HSIN ). The PLL includes a Phase-Frequency Detector, a Loop Filter, and a voltage controlled oscillator (VCO). All the Rx internal clock signals are generated from a Clock Generator that is driven by either the internal VCO or an external signal, TSTCLK, depending on whether both RXDIV1/0 are set high. Rx Phase-Lock Loop A detailed block diagram for the Rx Phase Lock Loop is shown in Figure 11. A frequency detector locks the VCO to the reference clock. Once this is achieved, a lock indication engages the phase detector, which maintains phase lock of the high speed incoming bits to that of the internal bit clock. The integrator, which requires one external capacitor, controls the frequency of the VCO. The output of the VCO is fed into a
Range Selector block, which further divides the VCO clock to the bit rate clock. The RXDIV1/0 inputs select between divide by 1, 2, or 4 ranges, as well as a test clock bypass mode. The bit rate clock then drives the clock generator, which provides clocks to the entire chip. Rx Decoding In Figure 4, the word demultiplexer de-serializes the recovered serial data from the Input Sampler, and outputs the resulting parallel data one word at a time. Every word is composed of a 16-bit Word Field (W-Field) and a 4-bit Coding Field (C-Field). The C-Field (c0-c3) together with the two center bits of the W-Field (w7 and w8) are then decoded by the C-Field decoder to determine the content of the word. The W-Field decoder is controlled by the outputs of the C-Field decoder. If an inverted Data Word or Control Word is detected, the W-Field decoder will automatically invert the W-Field data. If a Control Word is detected, the W-Field decoder will shift the bottom half of the W-Field so that the outputs are at pins RX[0-13]. RXDATA = 1 indicates that data word is detected by the receiver. RXCNTL = 1 indicates that a control word is detected by the receiver. An idle word is detected by the receiver if RXDATA = 0, RXCNTL = 0, and RXERROR = 0.
Rx Operation Principles The HDMP-1034A (Rx) is implemented monolithically in a high performance 25 GHz ft silicon bipolar process. The Rx accepts a serial stream of 20 bit Conditional Invert with Master Transition (CIMT) line code words and outputs parallel 16 bit/17 bit Data Words or 14 bit Control Words. The Rx performs the following functions for link operation: * Frequency Lock * Phase Lock * Word Synchronization * Demultiplexing
TSTCLK EXTERNAL CAP HSIN INTERNAL CLOCKS REFCLK FREQUENCY DETECTOR PHASE DETECTOR
1 0 LOCK
LOOP FILTER
VCO
DIVIDE BY N
CLOCK GENERATOR
INTERNAL CLOCKS
RXDIV1/0
Figure 11. HDMP-1034A (Rx) Phase-Lock Loop.
25
Integrator Capacitor and Supply Bypassing/Grounding Figure 12 shows the PLL integrator capacitors, power supply capacitors and required grounding for the Tx and Rx chips. Integrator Capacitor An integrator capacitor (C2) is required by both the Tx and Rx for them to function properly. This cap is used by the PLL for frequency and phase lock, and directly sets the stability and lockup times. A 0.1 F capacitor is recommended for each DIV1/0 setting. Supply Bypassing/Grounding The HDMP-1032A/34A chipset has been tested to work well with a single power plane, assuming that it is a fairly clean power plane.
As a result, all of the separate power supplies (VCC, VCC_TTL, and VCC_HS) can be connected onto this plane. The bypassing of VCC to ground should be done with a 0.1 F capacitor (C1). TTL and HighSpeed I/O I-TTL and O-TTL These I/O pins are TTL compatible. A simplified schematic diagram of the I/O cells is shown in Figure 13. High-Speed Interface: HS_IN and HS_OUT The simplified schematic diagrams of HS_IN and HS_OUT are shown in Figure 14. The HS_IN input cell is implemented with internal 50 resistors between the differential input lines HSIN to GND_HS.
The HSIN inputs have internal bias provided and the signals are AC coupled in with 0.1F capacitors. It is recommended that differential signals be applied across the HSIN inputs (Figure 15a), although a single-ended connection is acceptable. In this case, the unused input must be terminated with 50 AC coupled to ground. The HS_OUT output cell is designed to deliver PECL swings directly into 50. The output impedance is matched to 50 and has a VSWR of less than 2:1 to above 2 GHz. This output is ideal for driving the HS_IN input through a 50 cable and a 0.1 F coupling capacitor. The HS_OUT driver can also be
VCC_A2
C1 C1 C1
C1
C1 C1
C1
HDMP-1032A Tx
C1
HDMP-1034A Rx
C1
C1
C1
C2
C1
C2
C1
C1
C1
C1
C1
VCC_A1
VCC_A
C1 = BYPASS CAPACITOR C2 = PLL INTEGRATOR CAPACITOR
0.1 F 0.1 F
NOTE: VCC_A PINS SUPPLY VOLTAGE SHOULD COME FROM A LOW NOISE SOURCE.
Figure 12. HDMP-1032A (Tx) and HDMP-1034A (Rx) Power Supply Pins.
26
connected directly into a highspeed 50 oscilloscope. For optimum performance, both outputs should see the same impedance. It is necessary that all HS_OUT outputs be terminated into 50. Figure 15 shows various methods of interfacing HS_OUT to HS_IN and standard PECL logic.
Data Bus Line/Broadcast Transmission The GND_HS pins are normally tied to ground to provide 50 input impedance. For 1:N broadcast applications, 18K series resistors can be inserted between GND_HS and -5V to provide an effective high impedance as shown in Figure 16. A Port-Bypass Circuit (PBC) can also be used in a broadI_TTL
cast application as shown in Figure 17. Each input and output PBC is a dedicated channel and impedance matched to the transmission line. This is a superior method of achieving a broadcast mode compared to Figure 16, but does add an additional IC. More receivers can be added by cascading PBC ICs or using a PBC with more ports.
O_TTL ESD PROTECTION VCC VCC_TTL ESD PROTECTION
VCC
1.4 V
GND_TTL GND GND
Figure 13. O-TTL and I-TTL Simplified Circuit Schematic.
HS_OUT ESD PROTECTION VCC ESD PROTECTION VCC HS_IN
0.1 F
0.1 F ZO = 50 50 50
GND
GND_HS
GND
Figure 14. HS_OUT and HS_IN Simplified Circuit Schematic. 27
PECL OUTPUT
HSOUT+ Tx HDMP-1032A HSOUT--
50
0.1 F
HSIN+ Rx HDMP-1034A
Z0
0.1 F
HSIN+ Rx HDMP-1034A
50
0.1 F
HSIN--
R1 R1
Z0
0.1 F
HSIN--
A) G-LINK Tx TO Rx INTERCONNECTION NOTE THAT NO EXTERNAL TERMINATIONS OR BIAS RESISTORS ARE REQUIRED.
C) GENERIC PECL OUTPUT TO G-LINK Rx INPUT RESISTOR VALUE R1 SETS PROPER BIAS FOR THE PECL OUTPUT STAGE. THE G-LINK Rx IS INTERNALLY TERMINATED AND DOESN'T REQUIRE EXTERNAL BIAS OR TERMINATION RESISTORS.
+VCC
+5 V
0.1 F R1 HSOUT+ Tx HDMP-1032A HSOUT-- Z0 0.1 F R2 R2 _ Z0 0.1 F + R1 PECL INPUT
0.1 F 68 HSOUT+ Tx HDMP-1032A HSOUT-- 50 0.1 F 191 191 50 0.1 F 68
OPTICAL TRANSCEIVER (+5 V) TD+
TD--
B) DIFFERENTIAL DRIVE TO GENERIC PECL INPUT THE THEVENIN EQUIVALENT RESISTANCE IS EQUAL TO THE TRANSMISSION LINE IMPEDANCE (Z0) AND PROVIDES PROPER DC BIAS TO THE PECL INPUTS.
HSIN+ Rx HDMP-1034A HSIN--
50
0.1 F RD+
50
0.1 F 270 270
RD--
D) G-LINK INTERFACE TO OPTICAL TRANSCEIVER
Figure 15. Methods of Interfacing HS_OUT and HS_IN.
28
HSOUT+ Tx HDMP-1032A
0.1 F
50
50
50
50 100
HSOUT--0.1 F Rs Rs Rs Rs Rs Rs
Zstub
Zstub
Zstub
0.1 F Rb --5 V 20
0.1 F Rb 17
0.1 F Rb --5 V --5 V 20
0.1 F Rb 17
0.1 F Rb --5 V --5 V 20
0.1 F Rb 17 --5 V
Rx #1 HDMP-1034A
Rx #2 HDMP-1034A
Rx #N HDMP-1034A
NOTES: Rs (DAMPING RESISTOR) = 50 Rb (BIAS RESISTOR) = 18 K Zstub = 50 OR HIGHER, AND NO LONGER THAN 2.54 CM (1 INCH) THE 18 K RESISTOR TO --5 V BIAS THE Rx INPUT AND ALLOW HIGH-IMPEDANCE Rx INPUTS FOR 1:N BROADCAST APPLICATIONS.
Figure 16. Data Bus Line Transmission.
Rx #1 HDMP-1034A
Rx #2 HDMP-1034A
Rx #3 HDMP-1034A
Rx #4 HDMP-1034A
Rx #5 HDMP-1034A
Tx #1 HDMP-1032A
BYPASS[1]- = 0
BYPASS[2]- = 0
BYPASS[3]- = 0
BYPASS[4]- = 0
1 1 0 2
1 3 0
1 4 0
1 0 0
1 0
HDMP-0450
Figure 17. Broadcast Transmission using a HDMP-0450 Port-Bypass Circuit.
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BYPASS[0]- = 1
FM_NODE[1]
FM_NODE[2]
FM_NODE[3]
FM_NODE[4]
FM_NODE[0]
TO_NODE[1]
TO_NODE[2]
TO_NODE[3]
TO_NODE[4]
TO_NODE[0]
Nomenclature Changes between HDMP-1032A/34A and HDMP-1022/24 In previous versions of G-Link such as the HDMP-1022/24 each parallel unit of data was called a frame. This has been changed to a word with the HDMP-1032A/ 34A. Frame usually stands for a series of words that form a logical unit. For example, each unit of PPP unit is called a frame. It consists of a header and a checksum at the end. The encoded 20 bit entity for the HDMP-1022/24 was composed of a data field and also a control field. This was confusing because the data field contained data frames and control frames. In other words control and data were used in two different contexts which left the reader to identify which of the two meanings was meant. The encoded word was split into a word field and an encoding field.
With the HDMP-1032A/34A we have: * control words * data words * word field * where one may find control words or data words * encoding field In addition with the HDMP-1032A/ 34A, fill frames have been changed to idle words following the custom used in Fibre Channel and Gigabit Ethernet where idles are inserted if no information is being fed to the transmitter. Pin names have been changed to specify if they belong to the transmitter (Tx) or the receiver (Rx). In addition, some names have been changed to names analogous to those used in Fibre Channel and Gigabit Ethernet. Examples are TXCLK instead of STRBIN and RXCLK instead of STRBOUT. A pin cross reference table for the HDMP-1032A/34A & HDMP-1022/24 is provided in the table on the next page.
30
Pin Cross Reference Table
HDMP-1032A (Tx) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Name GND TX[14] TX[15] TXCNTL TXDATA TXFLAG NC VCC_TTL GND_TTL TXFLGENB ESMPXENB LOCKED VCC GND NC NC VCC_HS GND_HS HSOUTHSOUT+ NC NC NC VCC GND TXDIV0 TXDIV1 TCLKENB NC GND_A1 VCC_A1 TXCAP0 TXCAP1 NC GND VCC TXCLK NC NC GND_TTL VCC_TTL NC NC NC NC TX[0] TX[1] GND VCC TX[2] TX[3] TX[4] TX[5] TX[6] TX[7] GND_A2 VCC_A2 TX[8] TX[9] TX[10] TX[11] TX[12] TX[13] VCC HDMP-1022 (Rx) Name D14 D15 CAV* DAV* FLAG Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 HDMP-1034A (Rx) Name GND_TTL RX[1] RX[0] RXREADY RXERROR RXDSLIP VCC_TTL GND_TTL VCC GND REFCLK TSTCLK SHFIN SHFOUT SRQOUT VCC_HS GND_HS HSIN+ HSINGND_HS NC RXFLGENB ESMPXENB VCC GND PASSENB NC RXDIV0 RXDIV1 VCC_A GND_A RXCAP0 RXCAP1 SRQIN #RESET WSYNCDSB RXCLK0 RXCLK1 GND VCC GND_TTL VCC_TTL RXCNTL RXDATA RXFLAG RX[15] RX[14] GND_TTL VCC_TTL RX[13] RX[12] RX[11] RX[10] RX[9] RX[8] GND VCC_TTL RX[7] RX[6] RX[5] RX[4] RX[3] RX[2] VCC_TTL HDMP-1024 (Rx) Name D1 D0 LINKRDY* ERROR
FLAGSEL
TCLK
DOUT* DOUT
DIN DIN*
FLAGSEL
DIV0 DIV1 EHCLKSEL MDFSEL
TCLKSEL DIV0 DIV1
CAP0B CAP1B
CAP0B CAP1B
STRBIN
STRBOUT
D0 D1
CAV* DAV* FLAG D15 D14
D2 D3 D4 D5 D6 D7
D13 D12 D11 D10 D9 D8
D8 D9 D10 D11 D12 D13
D7 D6 D5 D4 D3 D2
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD).
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www.semiconductor.agilent.com Data subject to change. Copyright (c) 2001 Agilent Technologies, Inc. August 16, 2001 5988-3852EN

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